Semiconductor memory units embedded within an integrated circuit (IC) system are arranged in arrays of cells, where each cell stores one bit of information (1 or 0). Generally, in order to maintain the integrity of the data stored within an embedded semiconductor memory unit, such as an embedded dynamic random access memory unit (eDRAM), each cell of the memory unit requires periodic refreshing, since a small charge stored in each cell of the memory unit tends to leak off due to several factors, such as an increase in the temperature of the chip. Accordingly, circuitry is required to manage or control such semiconductor memory units for refreshing the cells. Hence, these circuits consume power causing a reduction in the lifetime of the battery when these circuits are utilized in hand-held, battery-operated devices.
For instance, the refresh circuitry generally includes several charge circuits which need to be activated to provide different voltage and current supplies to cells and other circuits of the memory unit. These charge circuits consume power which can significantly reduce battery lifetime. Additionally, the consumption of power by these charge circuits causes the chip temperature to increase, thereby decreasing the period of time between refresh cycles of the charge circuits. This further causes a reduction in the battery lifetime, since the charge circuits are activated at a greater frequency.
Furthermore, a respective constant-speed ring oscillator provided in proximity or within the memory unit is generally used to run these charge circuits. A typical frequency range for the oscillator is from 5 MHZ to 50 MHZ depending on the voltage or current required to be produced by the particular charge circuit. Hence, additional power is required to operate the constant-speed ring oscillators.
Since the charge circuits consume a relatively large amount of power, memory units are generally designed with a few or no additional circuits for adding additional features to the memory unit, such as band-gap reference circuit for providing a band-gap reference voltage, and a temperature sensor circuit for approximating the chip temperature. Further, when these additional circuits are added to the memory unit, they not only consume a great amount of power, but, as a consequence of consuming a great amount of power, they further facilitate the increase in the chip temperature. As indicated above, an increase in the chip temperature causes a decrease in the period of time between refresh cycles of the charge circuits, thereby causing the charge circuits to be activated at a greater frequency and consequently, draining the battery at a more rapid rate.
Further, these additional circuits are generally not designed to operate during low-power applications, especially when the supply voltage drops under one volt (a “sub-one voltage”), such that these circuits may be insensitive to the supply voltage. A paper published by Toshiba, Inc. in the IEEE Journal of Solid State Circuits, vol. 34, no. 5, page 670, May 1999, proposes a circuit to produce a CMOS band-gap reference voltage (Vref), where the circuit is capable of operating with a sub-one volt supply voltage. The paper discusses combining two current flows, one having a positive temperature coefficient and one having a negative temperature coefficient, and converting them to a reference voltage. However, the paper does not teach or discuss how to operate the proposed circuit in a low-power mode.